Cornelius Robinson (@CorneliusWrites) header
Cornelius Robinson (@CorneliusWrites) profile picture

Electronics and PCB design concepts, explained in animation daily. Builder of @GetAlignedApp. LDS. KG7VYL

Washington, USA
Joined March 2022
A 100 nF next to a 10 µF is classic decoupling, but the pair hides a peak. Between their two dips, the 10 µF already acts like an inductor while the 100 nF still acts like a capacitor, so they resonate. In this model: 154 mΩ at 11 MHz, 5× higher than 10 µF + 1 µF.
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When a high speed signal drops from the top layer to layer 3 through a normal via, the barrel doesn't stop at layer 3. The leftover bit below is a stub, and it's a dead end: part of every fast edge runs down it, bounces off the bottom and comes back as an echo.
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That 4.7 µF ceramic cap on your 12 V rail probably isn't 4.7 µF. Ceramic caps lose capacitance under DC voltage, and the same part in a bigger package holds on to a lot more of it. At 3.3 V the effect is much smaller for parts rated well above that, like these 16 V caps.
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If your board's clock drifts ahead, check the crystal's load caps. A 32.768 kHz crystal whose datasheet says CL = 12.5 pF doesn't want 12.5 pF caps: they sit in series, so it sees half that plus stray. With typical numbers it runs 40 ppm fast, gaining 1min 44s per month.
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I’ll say it. Patch panels are pointless and just decrease signal integrity. It’s easy enough to reconfigure the VLAN for any output.
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If you've put an ESP32 on a board, where it sits matters more than you'd think. Espressif tested one of their modules two ways: antenna past the board edge, and mid-board over copper. On channel 11, the mid-board one put out 6.9 dB less, about a fifth of the power.
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Ever had a ground pin that just won't solder? The plane is pulling the heat away. Same iron on two pads tied to GND: the solid connection took 4.6 s to melt the solder. With a thermal relief (4 thin spokes), 0.25 s. Your iron isn't weak. The plane is winning.
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Here’s an actual simulation that describes this effect. nitter.cf/michaelskywal/status/2…
Why won't solder flow through a ground pin? I simulated it on a 4-layer board. With a thermal relief, a 400 °C iron melts the solder on the far side in 3 seconds. Without one, you'd need 536 °C. A Hakko FX-888D only goes to 480. 🧵
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Where you put a buck converter's input cap matters. Each time the chip switches, current jumps around a loop. A longer loop rings harder due to the increased inductance. Keeping the input capacitor close reduces the ringing.
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An open via in an SMD pad is a tiny drain. A 0402 pad gets about 0.019 mm³ of solder from a 0.1 mm stencil, but a 0.25 mm via hole through a 1.6 mm board has room for 0.079 mm³, over 4× more. When the paste melts, the copper barrel wets and pulls the solder down.
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A ground strip beside a fast trace only shields if it's stitched. With a 100 ps edge and a quiet trace 1 mm away, no strip lets 5.8% of the signal couple over. A strip with one via rings and makes it worse: 6.4%. Add a via every 5 mm and it drops to 2.8%.
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Electrostatic discharges can easily damage sensitive semiconductors. An 8 kV zap ramps to 30 A in under a nanosecond. Put the TVS on a 12 mm stub with a long run to ground, and that ~10 nH adds ~390 V arrives that at the chip. A Diode right at the connector: ~47 V.
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Your 1 oz copper trace is about 35 µm deep. At 1 GHz, the current lives in a thin layer about 2 µm deep. This is called the skin effect. As frequency rises, current crowds toward the surface. By 1 GHz, only ~9% of the trace's copper is doing any work.
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Your 100 nF decoupling cap stops being a capacitor at higher frequencies. It filters best around 16 MHz. Above that, the inductance of its pads and vias takes over and it acts like an inductor. By 1 GHz it's about 200× worse than at its best.
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Why? A real cap is C + ESR + ESL in series. Its impedance dips to just the ESR at f = 1/(2π√(LC)). With 1 nH mounted, that's 16 MHz. Put it farther away and you add inductance: at 3 nH the dip slides down to 9 MHz. That's why decoupling caps go right next to the pin.
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What one button press looks like on an oscilloscope (simulated). Your code saw 6 presses. Metal contacts bounce for about a millisecond before they settle, and the pin sees every bounce. A 100 nF cap can't recharge between bounces, so only one press gets through.
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Your I2C pull-up sets your bus speed. Chips pull the line low fast, but only the resistor pulls it back up. Every pin and trace on the bus is a capacitor it has to charge.
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This is incredible
New Tesla Roadster just broke the entire internet. WHAT THE
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In a differential pair, every bend puts one trace on the inside, which ends up shorter. Two turns at 20 mil pitch ends up being about 63 mil shorter and ~10 ps early. Now the halves don't cancel, and that leaks out as noise and EMI. A small serpentine adds the length back
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Why it matters: A diff pair works because both halves switch at the same instant. If one edge shows up early, the two halves stop cancelling. You get common-mode noise, more EMI, and less margin at the receiver.
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