Comms Director at Intel. Boilers, Sounders, Cubs.
Washington
Joined April 2009
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"There is an important difference between technologies made in America and technologies that are truly American-made. The difference lies in the research and development process that transforms ideas into manufacturable technologies."
Building semiconductor leadership requires both innovation and the manufacturing capacity to bring it to scale.
In his latest piece, Naga Chandrasekaran highlights Intel Foundry’s growing U.S. footprint, including progress on our Ohio site.
Read more: ms.spr.ly/6010avfyk
#IntelFoundry
John Hipsher retweeted
Physical AI gets interesting when you can see what changes for people. @Intel + @SAP connected warehouse workflows with autonomous robots powered by Intel edge AI, reducing transport distance and repetitive manual handling. intel.com/content/www/us/en/…
"Intel says its technologies can currently scale packages to eight times the industry-standard reticle limit, with plans to exceed 12 times that limit by 2028."
packagingoem.com/larger-ai-c…
"The PDK 0.9 gives customers the confidence to design products on Intel 14A, as the technology is reaching the industry-standard performance and yield maturity expected at this stage of development, supported by silicon-backed validation."
intel.com/content/www/us/en/…
Great EMIB conversation between @austinsemis and Ravi Mahajan. Favorite quote:
"This was almost science fiction because the bridge I was talking about is roughly half the thickness of an A4 sheet of paper. So imagine being able to manipulate tiny strips of silicon like that."
🎙️ NEW EPISODE: How Intel Took EMIB From Science Fiction to High Volume: Intel Foundry's Ravi Mahajan
Ravi Mahajan, a distinguished engineer at Intel Foundry, joins Austin to detail EMIB's 20-year journey from a "science fiction" concept to a high-volume manufacturing reality.
- Organic package wire escape density at the die edge improved only about 10% per generation, so EMIB puts fine-pitch silicon in small patches at the die edges and leaves power to the substrate's thick metal
- Production required five technologies to converge, including a custom 4-layer silicon process and dies half the thickness of an A4 sheet of paper
- HBM was the first driver. Solve the highest-performance memory interconnect and the technology can "waterfall down" to everything else
- The advantage over CoWoS is manufacturing scale. Small bridges replace a full-sized silicon interposer and its high cost and poor wafer utilization on large, multi-reticle AI packages
- EMIB-T was in the original patent, using TSVs to fix the "torturous" power path around the bridge
- EMIB is an Intel Foundry exclusive, and the roadmap includes top-side optics
This episode is presented by @CrusoeAI. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: semidoped.com/crusoe-x
Chapters:
0:00 Intro: Ravi Mahajan
1:44 Pathfinding & The HIR Roadmap
7:58 The Two Drivers of EMIB
15:15 Decoupling I/O and Power
16:27 The 'Science Fiction' of EMIB
20:36 HBM as the Killer App
25:06 EMIB vs. CoWoS
31:44 Chiplets, UCIe, and Packaging Tiers
34:08 The EMIB Portfolio: T, M, Active
37:01 An Intel Foundry Exclusive
41:21 AI's Role in Packaging
43:26 Future: Top-Side Optics
Get more of Austin and Vik daily, free!
Sign up: daily.semidoped.com/
Connect with Vik and Austin:
Vik's Paid Substack: viksnewsletter.com
Austin's Paid Substack: chipstrat.com
@austinsemis @vikramskr @Intel_Foundry
John Hipsher retweeted
This was one of the most enjoyable media visits ever. Not just because Dwarkesh and his team were super kind and curious, but because they approached the topics in a way that filled a big hole in public knowledge of how these technologies come together.
In July, the @Intel_Foundry team hosted @dwarkesh_sp & his team at Intel Oregon for a multi-day shoot in and out of facilities. From R&D to front & back-end fabs, this was an all hands on deck moment for @intel. So proud to see this go live! @magicsilicon youtu.be/frYSOKvNiiE
John Hipsher retweeted
In July, the @Intel_Foundry team hosted @dwarkesh_sp & his team at Intel Oregon for a multi-day shoot in and out of facilities. From R&D to front & back-end fabs, this was an all hands on deck moment for @intel. So proud to see this go live! @magicsilicon youtu.be/frYSOKvNiiE
ICYMI
“This is what’s possible when we invent, develop and manufacture leading-edge semiconductors in America. The result is innovation that improves lives around the world.”
intel.com/content/www/us/en/…
Precision at an extraordinary scale. Foveros Direct 3D uses Cu-to-Cu hybrid bonding to achieve sub 10 µm pitch, with up to 10x finer interconnect density than conventional microbump technologies.
More in our technology brief: intel.com/content/dam/www/ce…
Advancing semiconductor performance isn't just about smaller transistors.
Innovations in advanced packaging, like hybrid bonding, enable denser chip-to-chip connections and create new opportunities for performance and power efficiency. But bringing these technologies to life requires extraordinary manufacturing precision.
Discover the engineering behind next-generation semiconductor packaging.
Watch the full conversation: ms.spr.ly/6011axei1
#IntelFoundry
John Hipsher retweeted
I found it really interesting to discuss how differently the history of semiconductor technology could have turned out if a butterfly had flapped its wings in the '60s.
Chris Auth, who leads Intel's process development, implied that all the counterfactual tech trees would have converged to around the same design by 2045:
3D structures of layers upon layers of transistors, with layers of connecting wires between each one.
And that this is basically where we're headed over the next 10 to 20 years as well .
This is what great technology storytelling looks like. Deeply curious, technical and willing to put in the time to understand how things actually work.
Glad to have been a part of this.
I spent two days touring Intel’s most advanced fab and talking to its technical leadership to understand what the chips of the future will look like.
A lot of what's coming next – gate-all-around transistors, backside power, CFET, hybrid bonding – is hard to follow without actually seeing it, so we made all the awesome animated explainers that I wish I had while I was prepping.
I also asked Intel’s leadership how the semiconductor industry will cope with the enormous shock in demand from AI.
AI compute has grown 3x a year for the last decade, but according to Intel's CTO, Intel could only double leading-edge wafer production with today’s global stock of chipmaking tools.
What kinds of tricks can foundries pull to extend this crossover point where demand surges way ahead of supply?
This was a totally new format for us - hope you enjoy!
0:00:00 – Intro
0:00:47 – How Intel brings up a new process node
0:03:22 – What Intel learned from 10nm
0:06:28 – From planar transistors to gate-all-around
0:13:13 – Why High-NA EUV pays off for Intel but not TSMC
0:19:20 – Could chips have evolved completely differently?
0:23:33 – Inside Intel's "Hot Topics" meeting
0:29:30 – Replacing copper wires with ruthenium
0:32:41 – Why stacked transistors take a decade to ship
0:39:45 – Hybrid bonding and the chip-to-chip bottleneck
0:48:00 – There aren't enough tools to 10x chip production
0:53:14 – Can Intel catch up to TSMC?
1:01:02 – Terafab, and rethinking the fab from scratch
John Hipsher retweeted
What does it really take to make the world's most advanced chips?
Thousands of intricate manufacturing steps. Extraordinary engineering precision. And an industry working to meet growing global demand for computing.
Get an inside look at Intel's semiconductor innovation as Chris Auth, Pushkar Ranade, and other Intel experts join @dwarkeshpodcast to explore the science, technology, and manufacturing expertise behind advanced chips.
Watch the full conversation: ms.spr.ly/6014aaFMm
John Hipsher retweeted
$INTC Foundry will become foundational to leading edge chip manufacturing over the next decade. So much Intel value will be unlocked as it ramps. 👀
Building semiconductor leadership requires both innovation and the manufacturing capacity to bring it to scale.
In his latest piece, Naga Chandrasekaran highlights Intel Foundry’s growing U.S. footprint, including progress on our Ohio site.
Read more: ms.spr.ly/6010avfyk
#IntelFoundry
John Hipsher retweeted
Intel Oregon employs more than 15K people doing cutting edge R&D for American process technologies. The only US company doing so. (Volume production in Arizona/NM/Ohio employees even more)
TSMC Arizona after their 6 Fab buildout is done in the early 2030s in Arizona plans to employ 12,500.
R&D is by far the biggest driver of employment and continuous investment than importing foreign technologies.
$INTC
John Hipsher retweeted
Building semiconductor leadership requires innovation and the manufacturing capacity to bring it to scale.
In a new piece, Naga Chandrasekaran shares how Intel Foundry is expanding that capacity across the U.S., including progress on our Ohio site, where the initial major structural truss has been installed on first fab.
Read more: ms.spr.ly/6015aauoh
John Hipsher retweeted
Arizona continues to prove why it's a top destination for semiconductors 🌵
Great to join @AZChamber & industry leaders celebrate the momentum driving Arizona’s manufacturing sector. From workforce to tech innovation, the future is being built right here. Proud to be part of it.
John Hipsher retweeted
Naga $INTC holding court at @Applied4Tech EPIC Center opening after recently signing on.
Why join Samsung and TSMC as a founding partner one week ago risking IP leakage?
“We are now having to look at the innovation at a system level. We need to look at customer expectations, translate that back down to an atomic level, and now start developing and delivering to the customer at a very fast pace, and it cannot happen just inside the factory walls. It cannot happen just inside the individual companies that we operate with. It has to happen as a collaborative ecosystem.”
“We are starting to look at multiple chiplets put on these substrates and scaling the substrate size from what used to be two to 3x reticle size to now 9x and maybe even 12x as we look at the future, and that's driving a whole supply chain and ecosystem-level innovation right now.”
“Our customers want innovation every year.”
John Hipsher retweeted
Today we call it “Purpose-Built Silicon”
On October 6, 1986, Intel expanded its commitment to the ASIC (Application-Specific Integrated Circuit) market, building custom-designed chips built to meet the specific needs of a particular application.
As we mark this 40-year milestone, we celebrate the employees whose vision, ingenuity, and determination helped shape this important chapter in Intel's history.
From the pioneers who launched Intel's ASIC efforts to those who continued building on that foundation, thank you for your contributions and lasting impact.
John Hipsher retweeted
AI is moving fast. Semiconductor innovation has to keep pace.
@Intel and @Applied4Tech are deepening our technical collaboration across transistors, interconnects, and advanced packaging to move innovation from R&D to manufacturing faster. ir.appliedmaterials.com/news…