#HIPEACInfo79 is out! Apart from quantum computing, you can read about events & projects we are involved in, such as #ACACES, SwissChips & the best paper at EuroMicro DSD: hipeac.net/news/magazine/717…. Wishing you a nice weekend!
We introduce "RTSM: Adapting Recursive Models to Multivariate Time-Series Classification" through a learned temporal tokenizer, single-state weight-tied refinement & a pooled sequence-level readout. See our paper arxiv.org/abs/2610.23353
PULP Platform retweeted
We need a strong suite of silicon proven open source designs, and here it is!
We are delighted to announce the launch of the PULP benchmark suite. github.com/pulp-platform/eda…. It is a collection of practical SystemVerilog designs, with a basic synthesis script with Yosys, a file list, Verilator support & SDC files for ASAP7. Prepared partly for ODE4EC project.
We are delighted to announce the launch of the PULP benchmark suite. github.com/pulp-platform/eda…. It is a collection of practical SystemVerilog designs, with a basic synthesis script with Yosys, a file list, Verilator support & SDC files for ASAP7. Prepared partly for ODE4EC project.
We introduce Spatial-TRM, a compact recursive model with frozen vision-language features, a convex region decoder, and just 11.2M trainable parameters. Check out "Look, Reason, Draw a Region: Recursive Refinement for Spatial Context Prediction" arxiv.org/abs/2610.23302
PULP Platform retweeted
Monte Cimone v3 is a major leap forward in HW and SW maturity and competitiveness for the #RISCV HPC ecosystem! @e4company @Cineca1969
Assessing the competitiveness of #RISCV against established x86 and Arm processors is difficult. We address this problem in "Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads". See arxiv.org/pdf/2610.32632
Assessing the competitiveness of #RISCV against established x86 and Arm processors is difficult. We address this problem in "Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads". See arxiv.org/pdf/2610.32632
Check out now Tim's completed doctoral thesis "Scalable Interconnects for Integrated Accelerators" in the ETH Zurich Research Collection. See research-collection.ethz.ch/… @fischetim
You can now find and download Marco's PhD thesis "Many-Core Programmable Clusters for Open, Software-Defined, and AI-Native Radio Access Networks" in the ETH Zurich Research Collection: research-collection.ethz.ch/… @MarcoBertuletti
We are delighted to introduce our new colleague Yuhan! Yuhan will be focusing his research on MAGIA platform integration and deployment for AI models. His research interests include computer architecture and AI accelerator design. Welcome to the team!
We are excited to present Thomy, the first chip we made with an openPDK ICsprout55. Check out asic.ethz.ch/2026/Thomy.html & github.com/openecos-projects….
Greetings from #CERN where we have Viviane and Jayanth attending the workshop on Brevitas to dive deep into neural network quantization!
You can now find Yichao's PhD thesis " Toward Thousand-Core Shared Memory: Scalable Many-Core Architectures for Data-Intensive Workloads" in the Research Collection of ETH Zurich: research-collection.ethz.ch/… @yichao_zh
Cédric, Marc-Andre & Sebastian recently participated at #IUS2026 in Raleigh presenting their work on wearable ultrasound. Check out their papers arxiv.org/abs/2610.01602, arxiv.org/abs/2610.06263, arxiv.org/abs/2610.01603, arxiv.org/abs/2610.01623. Have a great weekend!
Kai & Chen recently attended #BEC2026 taltech.ee/en/bec2026 in Tallinn, meeting with our partners from TalTech & TAICHIP, sharing their research. Kai presented 'PULP4SPACE: Developing Next-Generation Space Processing Platforms' at the TAICHIP special session.
Our new colleague Glenn recently attended #MICCAI2026 in Strasbourg where he presented "S-CEReBrO: Breaking the Memory Barrier in Continuous EEG Monitoring". Check out his paper here: arxiv.org/abs/2607.27913
A quick look back at the conference panel "AI as the Chip Designer: Evolution or Illusion?" that took place at #VLSISoC in Cyprus with Frank representing PULP. See vlsi-soc.com/program.html#pa… for details.
And here is Lorenzo who presented his work "Physically-Aware Preemptive Virtual Channels for Deadlock-Free AXI Networks-on-Chip" at #VLSISoC in Cyprus. Find the poster and slides here: pulp-platform.org/docs/vlsis… pulp-platform.org/docs/vlsis…
#VLSISoC is currently underway in Cyprus. Our Bowen is there presenting "Ventaglio: At-the-Roofline Sparse Tensor Contractions on Vector Processors for Transformer Inference". Check out his slides: pulp-platform.org/docs/vlsis…
Giusy's #IEEESMC2026 slides "A Wearable Multimodal Ultrasound+Inertial System for Real-Time Virtual Reality Interaction" are now online: pulp-platform.org/docs/smc20… See also arxiv.org/abs/2606.17741 & github.com/pulp-bio/wulpus & github.com/pulp-bio/biogui
