ElfMaster

I guess I can officially say that I "modified" CPU / ISA ;-) HWASAN on RISC-V is finally possible! Subjectively, I perceive it as my little success to make the @risc_v ecosystem more secure. After 4 years of my, @martin_maas and the entire J-ext group hard work, RISC-V Pointer Masking (PM) extension for ISA is finally ratified! Moreover, in the meantime we were working with the @risc_v committee to include not only PM but also another extension which I helped co-design, Control Flow Integrity (#CFI), as part of the RVA23 profile as well as optional extensions in RVB23. CFI is also an optional ISA extension for RVM23 profile. You can read the official announcement of ratification of RVA23 profile here: riscv.org/announcements/2024… Official RISC-V Control Flow Integrity Extension is available here: github.com/riscv/riscv-cfi/r… Official RISC-V Pointer Masking extension is available here: github.com/riscv/riscv-j-ext… Nevertheless, it doesn't stop here! Memory Tagging extension is in progress and hopefully more...