$TER $LITE $COHR $KEYS $AMKR WOW! TAIWAN'S NEW STATE CPO GRANTS GO TO ALIGNMENT AND TEST. THE CALL ITSELF SAYS TESTING CAN EAT 20–30% OF A MODULE'S COST TAIPEI, Oct. 6 — Taiwan's National Science and Technology Council has opened calls for two three-year university research programs, one on silicon photonics and co-packaged optics (CPO), the other on power conversion for next-generation AI data centers. The council's engineering department sent the calls out in a letter dated Oct. 2, universities began forwarding them on Oct. 6, and campus deadlines fall on Dec. 31. Funded projects would run from Aug. 1, 2027 to July 31, 2030. The photonics call is aimed at the packaging and assembly level, and its documents state plainly that chip design and wafer manufacturing are out of scope. The suggested target specs: - Fiber-to-chip alignment accuracy of ±0.5 µm, coupling loss under 1 dB - A 16-channel fiber array aligned in under 90 seconds on a demo line, under 60 seconds as a stretch goal - CPO packaging cycle under 120 seconds per module, yield above 85% - 800G to 1.6T module testing in under 60 seconds per module, 4 to 8 channels in parallel, more than 85% automated - CPO first-pass yield above 80% The documents say testing may account for 20% to 30% of module cost as demand for 800G and 1.6T data center modules rises, and that fiber-array coupling with external lasers, thermally stable packaging and testability are among the biggest obstacles to industrialization. They put CPO's power saving at roughly 60% versus pluggable optics in rack-to-rack (scale-out) links, and roughly 80% if it moves inside the rack (scale-up). They also describe 2026 as the year silicon photonics and CPO move from qualification into volume ramp, citing $NVDA's newsroom. Each team must sign a domestic company before applying and show its milestones at that partner's site or at the partner's customer. Funding is capped at NT$8 million a year per project, about US$252,000, and the program generally won't pay for large equipment. The power call is capped at NT$7 million a year and is designed for a DC bus above NVIDIA's 800 V. It assumes buses will rise to 1,200 V or 1,500 V and sets these targets: - A solid-state transformer taking 34 kV or 13.2 kV medium-voltage AC down to 1,200 V or 1,500 V DC, demonstrated above 12 kW, at 97% peak efficiency - A 1,200 V or 1,500 V to 54 V converter at 12 kW and 98% peak efficiency - A 54 V to 1.8 V stage delivering 100 A with a power-density goal of 1,000 W per cubic inch - A DC solid-state circuit breaker that opens in under 25 microseconds DIGITIMES reported the two programs on Oct. 6. I put the photonics call's supply-chain chart next to the U.S. optical and test names we follow. The chart, compiled by the council's semiconductor expert group, places $LITE and $COHR in the laser slot, $TER and $KEYS under test equipment, $AMKR and $GFS in CPO packaging, and $GLW under glass substrates. $AAOI and $FORM are not on it, and the probe-card slot goes to Taiwan's MPI (6223 TT). The chart says its list is not exhaustive. The grant won't pay for testers, so that equipment has to come from partners and existing labs, and on the chart's test-equipment row the only U.S. names are Teradyne and Keysight.