founding engineer @vicharak_in | asic & micro-arch
India
Joined November 2023
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I have finally submitted my first tapeout to wafer.space run2 shuttle
Its a Dual core Risc V based IO co-processor based on BIO Co processor from Andrew "Bunnie " 's Baochip- x1
Basically : Two PicoRV32 RISC-V cores, 4 KB of foundry SRAM across 8 hard macros, 32 bidirectional GPIO, clock gating, and an SPI slave interface ,all in a half-width die slot (1936 × 5122 µm).
Check it out :
#riscv #opensource #silicon #asic
Deepak Sharda retweeted
For anyone who wants to understand how TPUs or any typical AI inference accelerator function, Gati, our recently open-sourced architecture + source code with RTL, is a great example. Initially, we planned to monetise it on top of our FPGA boards. It represents almost 2 years of effort by a team of 10+ people and has everything: offloading weights, fetching them from DRAM, MMU controllers, special operator accelerator engines, etc.
For compiler devs, architecture devs, hardware devs or no matter what field you belong to, this will help you.
https://
github.com/vicharak-in/ga
ti_platform
PS - i've made claude generated animation video of how it works. there might be multiple errors but on an abstract way it explains how gati works.
Almost all of AI comes down to one step: multiply two numbers, add the result. Billions of times.
I wrote about how that step runs on gates, CPUs, GPUs and systolic arrays, and why we built Gati, our open source FPGA accelerator at @vicharak, the way we did.
It's a bit of a long read, but I hope it's worth it. Let me know your feedback.
blog.vicharak.in/gates-to-ga…
Chip #1 on this list, our single-core CORDIC from Tiny Tapeout, works. Just not at the SPI speed we planned. In mode 0 it tops out at 5 MHz.
Here's why.
The SPI slave was an oversampling design. SCK, MOSI and CS were sampled by the system clock through synchronizers, and edges were detected in logic. It's simple and it keeps everything in one clock domain.
The cost is latency. Every SCK edge takes 2–3 system clocks to reach the logic. In mode 0 the slave updates MISO after the falling edge, and the master samples it on the next rising edge. All of that latency, plus pad and I/O delay, has to fit in half an SCK period.
So the max SCK isn't set by how fast the logic is. It's set by the ratio to the system clock and the round trip through the pads. On Tiny Tapeout, that path also runs through the shared I/O mux.
What I'd do differently: clock the shift register directly from SCK and cross into the system domain once per word. Or at least write the SCK-to-sysclk ratio into the spec on day one, instead of discovering it on the bench.
Third: BIO-lite, a dual-core PicoRV32 coprocessor on wafer.space Run 2. Most of the pre-submission work was chasing X's in post-CTS gate-level sim: clock gating, reset sequencing, and one decode register that powered up undefined.
Its hard to see AI do my job better then me need to get serious skill upgrades , but model will become better as well so what to do now ? 🙁
Lessssssss go .
🚀 eChipHub–SCL MPW Shuttle Programme!
Turn chip designs into real silicon! 🇮🇳
Submit eligible designs using open-source EDA tools for fabrication at SCL Mohali (1.2 µm & 0.8 µm nodes).
📅 Deadline: 5 Dec 2026
🔗 lnkd.in/g5k5fhrP
#eChipHub #SCLMohali #ChipDesign
What if i make a opensource #riscv controller with a #tinygpu or a small #tpu embedded with it and tape-out on wafer.space .
Would you be interested in getting your hands on one ??
Off course you will have to pay 🥲
The amount of things I have tried , learnt and got done in last 2 years . If I put it on my resume people would thing I am lying.
Perks of working in a startup I think. 😶
Ahh I forgot we already made it .
@AksharVastarpar lets make something affordable with 4/8 k luts . Something for $10-15
Big brother of shrike .
