Investor @IntelCapital | Opinions are my own. Mavericks & Cowboys fan | Love Islay malts, freshly brewed coffee.
San Jose, CA
Joined November 2009
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Srini Ananth retweeted
🎙️ NEW EPISODE: How Intel Took EMIB From Science Fiction to High Volume: Intel Foundry's Ravi Mahajan
Ravi Mahajan, a distinguished engineer at Intel Foundry, joins Austin to detail EMIB's 20-year journey from a "science fiction" concept to a high-volume manufacturing reality.
- Organic package wire escape density at the die edge improved only about 10% per generation, so EMIB puts fine-pitch silicon in small patches at the die edges and leaves power to the substrate's thick metal
- Production required five technologies to converge, including a custom 4-layer silicon process and dies half the thickness of an A4 sheet of paper
- HBM was the first driver. Solve the highest-performance memory interconnect and the technology can "waterfall down" to everything else
- The advantage over CoWoS is manufacturing scale. Small bridges replace a full-sized silicon interposer and its high cost and poor wafer utilization on large, multi-reticle AI packages
- EMIB-T was in the original patent, using TSVs to fix the "torturous" power path around the bridge
- EMIB is an Intel Foundry exclusive, and the roadmap includes top-side optics
This episode is presented by @CrusoeAI. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: semidoped.com/crusoe-x
Chapters:
0:00 Intro: Ravi Mahajan
1:44 Pathfinding & The HIR Roadmap
7:58 The Two Drivers of EMIB
15:15 Decoupling I/O and Power
16:27 The 'Science Fiction' of EMIB
20:36 HBM as the Killer App
25:06 EMIB vs. CoWoS
31:44 Chiplets, UCIe, and Packaging Tiers
34:08 The EMIB Portfolio: T, M, Active
37:01 An Intel Foundry Exclusive
41:21 AI's Role in Packaging
43:26 Future: Top-Side Optics
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Austin's Paid Substack: chipstrat.com
@austinsemis @vikramskr @Intel_Foundry
Srini Ananth retweeted
I spent two days touring Intel’s most advanced fab and talking to its technical leadership to understand what the chips of the future will look like.
A lot of what's coming next – gate-all-around transistors, backside power, CFET, hybrid bonding – is hard to follow without actually seeing it, so we made all the awesome animated explainers that I wish I had while I was prepping.
I also asked Intel’s leadership how the semiconductor industry will cope with the enormous shock in demand from AI.
AI compute has grown 3x a year for the last decade, but according to Intel's CTO, Intel could only double leading-edge wafer production with today’s global stock of chipmaking tools.
What kinds of tricks can foundries pull to extend this crossover point where demand surges way ahead of supply?
This was a totally new format for us - hope you enjoy!
0:00:00 – Intro
0:00:47 – How Intel brings up a new process node
0:03:22 – What Intel learned from 10nm
0:06:28 – From planar transistors to gate-all-around
0:13:13 – Why High-NA EUV pays off for Intel but not TSMC
0:19:20 – Could chips have evolved completely differently?
0:23:33 – Inside Intel's "Hot Topics" meeting
0:29:30 – Replacing copper wires with ruthenium
0:32:41 – Why stacked transistors take a decade to ship
0:39:45 – Hybrid bonding and the chip-to-chip bottleneck
0:48:00 – There aren't enough tools to 10x chip production
0:53:14 – Can Intel catch up to TSMC?
1:01:02 – Terafab, and rethinking the fab from scratch
Since leading Mueon Corporation's seed round last year, we’ve watched the team do the difficult work of turning a first principles view of data center design into a working system platform.
Today, @MueonCorp announced $65M in Series A funding led by Maverick Silicon, with participation from Intel Capital. The company is moving its Cubelets 3D compute and memory architecture toward system validation and production, targeting up to 10X power and cost efficiency within the same rack footprint.
Read more from Phoebe Liu (@_pheebini) at @TheInformation:
theinformation.com/briefings…
Our conviction in the team has only grown, so we’re excited to participate in Mueon’s $65M Series A. This round reflects the engineering depth and ecosystem required to bring that vision to market.
1/ Kepler holds the record for the longest any of our portfolio companies has stayed in stealth: seven years.
2/ What has always been clear is the team's conviction in pursuing a foundational problem spanning materials, memory, and logic.
Today, after 7 years in stealth, I, @emeskey and our co-founders are proud to announce @keplercompute.
The world is much better off when we give power & intelligence to the people. When everyone can become their highest selves by pairing their human creativity with the exponentially rising intelligence from our magnificent computers.
Our goal is to unlock the power of frontier intelligence for everyone by pushing memory and logic chip manufacturing to the limits of physics.
To achieve this, we will move the world from one of compute scarcity to abundance where we can make orders of magnitude more chips per dollar and can lower datacenter energies to the limits of physics. We will use physics to ensure we have enough chips and that we can power them on.
Why is compute scarce?
Today's dominant approach - shrinking transistors with EUV - has run into $20B-$40B fabs that take years to build. Sized against that risk, the industry (quite rationally!) grows capex much slower than AI demand that can grow 10x in a year.
In the current system, scarcity is built in.
A different way is possible.
We founded Kepler on the following beliefs:
1. It is possible to build leadership chips without a dependence on EUV
2. It is possible to achieve multiple orders of magnitude more intelligence per watt by evolving chips 2D Silicon to 3D Beyond silicon
3. It is possible to get much closer to the physical limits of computing than we are today while staying within mainstream digital computing
Memory is the biggest binding constraint on AI compute and so we start with a new frontier of AI memory- approaching the bandwidth per watt of SRAM, going up to 10x beyond the capacity of HBM. We use 3D and materials innovations that allow for leapfrogging leading nodes while requiring no EUV lithography and allowing us use fabs that already exist.
Our team co-led one of the industry's first 3D chip-stacking technologies, has led and scaled seven generations of DRAM and multiple logic designs into billions of chips. We built the world's first commercial physical synthesis tool and techniques at the heart of the logic design industry and solved long standing challenges in ferroelectrics, invented beyond CMOS logic devices. We would love to work with you to reinvent chip manufacturing here in America.
We have raised $468m, built our own fab and our AI memories sample this year and ramp to production next year. We are allocated for 2027 and will be scaling in America by 2028.
We are open for business, please get in touch to work together. We are also growing the group of Keplerians and would love to work with you.
Learn More @ Kepler: keplercompute.com/
Read our story in @WIRED: wired.com/story/a-new-dollar…
3/ They made a deliberate choice to mature the technology and de-risk the path to manufacturing at scale before stepping into the spotlight.
4/ After years of hard work, it's exciting to finally see the story out in the open. Congratulations to @keplercompute team!
Srini Ananth retweeted
Today, after 7 years in stealth, I am proud to share the Kepler story with you. I and @dolaoseb @rajeevdokania Amrita Mathuriya Prof. Ramamoorthy Ramesh are proud to announce Kepler. I am humbled to work with the immense Kepler team.
Our goal is to unlock the power of frontier intelligence for everyone by pushing memory and logic chip manufacturing to the limits of physics. We went after the Moore's law fabric revival not because it was easy, but the right thing to do even if it was hard.
Our fabs are humming.
Our tools are printing SRAM.
Our HBM is powered on.
Our Logic is proven.
Our wafers are being stacked.
We are open for business.
Learn More @ Kepler: keplercompute.com/
Read our story in @WIRED: lnkd.in/gcak6EGc
Srini Ananth retweeted
Yesterday, @intel completed our planned capital raise of $20B in one of the largest follow-on equity offerings on record. With strong support from targeted long-term sovereign funds, fundamental growth and institutional investors, specialty hedge funds and retail investors, the round was oversubscribed >5X our initial goal.
Many thanks to our underwriters JP Morgan, Goldman Sachs, Morgan Stanley and Citigroup for their excellent support. With this additional capital, Intel is now well positioned to meet the tremendous growth opportunity ahead of us in advanced node wafer manufacturing, advanced packaging and the massive CPU demand. We remain laser focused on execution across all our businesses.
Along with the full support of our Board, my leadership team and I are fully committed to delivering strong returns to our shareholders in the coming years and to building a new and vibrant Intel.
Srini Ananth retweeted
Joby is partnering with @travisk’s Atoms to build America's vertiport network.
Today, Joby and Atoms announced a definitive agreement to develop next-generation transportation hubs where electric air taxis, autonomous ground vehicles, and ridesharing converge, anchored by GEACS, our open-source Global Electric Aviation Charging System.
The work starts in Florida, New York, and Texas, the markets where Joby is preparing to launch early operations under the White House-backed eVTOL Integration Pilot Program (eIPP), as well as California.
Full release ⬇️
Most surprising AI infrastructure story of 2026 might be Elon turning into a leading hyperscaler :)
Srini Ananth retweeted
Nvidia’s primary moat is its proprietary software CUDA. DeepSeek is challenging that in China with Huawei chips, and Zyphra is challenging it in the West with AMD.
Forbes: "San Francisco-based Zyphra develops advanced, open-weight artificial intelligence models and offers cloud infrastructure services. While most AI labs still default to Nvidia chips, Zyphra says it trains and runs inference for its models entirely on AMD hardware—pitching that as both a cost and supply-chain advantage. In recent months, investors have been increasingly interested in funding U.S.-based alternatives to DeepSeek."
— from: forbes.com/sites/annatong/20…
+ Benchmarking of Zyphra-AMD vs. Nvidia B200 below...
We're publishing our first end-to-end benchmarks for Zyphra Inference on @AMD Instinct MI355X.
Our inference optimizations strongly outperform the AMD baseline and narrows the gap between MI355X and B200 for serving Kimi K2.6, GLM 5.1, and DeepSeek V3.2 🧵
Srini Ananth retweeted
I've been saying
Zyphra is an exceptional neolab, on all levels from moral to technical to financial. They have done what Geohot has failed to do: made AMD relevant again. They'll reap the rewards for it.
Truly, DeepSeek of the West
Today we’re announcing 15MW of AMD Instinct MI355 GPU capacity through Zyphra Cloud, our full-stack neocloud powered by @AMD.
Srini Ananth retweeted
Today we're releasing ZAYA1-VL-8B, our first vision-language model.
ZAYA1-VL-8B is a 700M active / 8B total MoE built on our ZAYA1-8B base trained on @AMD. We achieve strong performance for our size resulting in leading intelligence density and inference efficiency.
Srini Ananth retweeted
Zyphra remains one of my favorite teams in the game because the releases all point in the same direction: capable AI that is cheaper to train, cheaper to run, and easier to deploy across modalities.
ZAYA1-8B is the latest proof point for that pattern, extending Zyphra’s all-AMD ZAYA1 stack into post-training.
The base model showed AMD Instinct MI300 hardware could train a competitive MoE. ZAYA1-8B was pretrained, midtrained, and SFT’d on a 1,024-node MI300X cluster with AMD Pensando Pollara interconnect built with IBM. This release shows the reasoning side: 8.4B total parameters, only 760M active, trained end-to-end by Zyphra, then pushed into math/code-heavy reasoning where it competes with much larger open reasoning models.
The key is active-parameter efficiency. ZAYA1-8B is not a dense 8B; it is a small MoE with sub-1B active compute per token. Architecturally, Zyphra changed three pieces versus a standard MoE: Compressed Convolutional Attention for sequence mixing in a compressed latent space with 8× KV-cache compression, an MLP-based router with PID-controller bias balancing, and learned residual scaling.
The training recipe is the other major piece: ZAYA1-8B was trained from scratch for reasoning, with long-CoT data included from pretraining onward using answer-preserving trimming. Post-training then runs SFT followed by a four-stage RL cascade: reasoning warmup on math and puzzles, a 400-task RLVE-Gym adaptive curriculum, math/code RL with TTC traces and synthetic code environments, then behavioral RL for chat and instruction following.
The test-time-compute piece is Markovian RSA: multiple traces are generated in parallel, fixed-length tail segments are carried forward, and recursive aggregation prompts seed the next round. The point is bounded context during extended reasoning: with the 40K/4K configuration, ZAYA1-8B reaches 91.9 on AIME’25 and 89.6 on HMMT’25 while forwarding only a 4K-token tail.
Outside the TTC setup, what stands out is the reasoning density: AIME’26 89.1, HMMT Feb.’26 71.6, IMO-AnswerBench 59.3, LiveCodeBench-v6 65.8, GPQA-Diamond 71.0, and MMLU-Pro 74.2 from a 760M-active / 8.4B-total MoE.
ZAYA1-8B is the small-active MoE reasoning recipe in practice: sparse active compute, efficient inference, and enough reasoning density to make local and test-time-compute deployments interesting.
Today we're releasing ZAYA1-8B, a reasoning MoE trained on @AMD and optimized for intelligence density.
With <1B active params, it outperforms open-weight models many times its size on math and reasoning, closing in on DeepSeek-V3.2 and GPT-5-High with test-time compute. 🧵
Srini Ananth retweeted
More broadly, ZAYA is a demonstration of the full-stack philosophy of Zyphra, with innovations in architecture, pretraining, post-training, and inference coming together to produce a powerful model. I am immensely proud of the team. Keep your eyes peeled for later this week.
Srini Ananth retweeted
So happy about this release. Zyphra is still sandbagging a little – doing small models – but here, everything else comes together. Their SoTA architecture ("DSMoE-MLA++"), high-end RL and test-time scaling. Frontier open lab, talented and brave. Best of the West.
80B upcoming.
Today we're releasing ZAYA1-8B, a reasoning MoE trained on @AMD and optimized for intelligence density.
With <1B active params, it outperforms open-weight models many times its size on math and reasoning, closing in on DeepSeek-V3.2 and GPT-5-High with test-time compute. 🧵