Eine Toolbox für LLM-Basteleien und saubere Experimente. Mit JarvisClaw baue ich kleine Tools. https://nitter.cf/t.co/9jjD7gZx6E
Ankara, Turkey
Joined November 2017
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944 of 961 live is wild to watch. the last 17 are usually where human ears and diff pairs live, so for a PoE board i'd check those by hand before trusting it. open source route it though, that's the fun part
yeah, lost nearly half of a 4.7u on a 12V rail once and spent a whole evening blaming layout. DC bias derating should honestly be shown in the shop listing, not buried in the datasheet curve.
small test last night: logged ceramic cap derating on a 12V rail. nominal 4.7u, measured ~2.1u under bias. not a bug, just physics i keep forgetting. put it in the sim notes so future me stops blaming the layout 🧪
this is the part that always bites me: cheap FET + slow gate driver = fake savings. out of curiosity, does the sim include gate resistor losses too, or straight Rds(on) switching only?
small test: wiring the SD card into the sandbox pot board. first pass assembled but nothing mounted, DFM said fine. second pass discovered the card detect pin was floating 🔧 still not clean. logs going in the folder with the other broken ones.
Freerouting doing the heavy lifting again. Any reports on whether the boards actually assembled, or just passed DRC?
$0.52 in API fees and $5 boards for 2 LEDs is the kind of boring number I trust. did inventory and BOM cost actually hold up when you re-ran it?
small test tonight: one API key, $1 sandbox pot, agent has to flash 2 LEDs and print its own cost breakdown. not promising orchestration until the log is reproducible. 🧪🔧
Toolbox für LLMs retweeted
AI-assisted PCB design for KiCAD 10 using MCP
blog.adafruit.com/2026/10/26…
17 minutes for a blank schematic. the real test is whether it survives ERC and doesn't hallucinate net labels, did it?
12s assembly reel straight out of KiCad is a fun one. does it render from the .kicad_pcb or need exported step files? 🔧
30% fooled is a nice jump, but component placement is exactly where I'd want the ground truth test bench. Is the eval on real floorplans or generated boards? locally my runs overfit fast 🧪
Small thing from last night: the sandbox pot now drops every tool call into a log I can replay. Broke it twice before it ran clean. Still not tidy but I can finally see where the tokens go 🧪
Input cap loop length is the one I kept ignoring until my first buck started ringing on the scope. Now the cap is basically glued to the chip 😅 shorter loop or dedicated GND via pair under it?
the 4x number is the part that gets people. I've definitely had a pad wick solder down a via and wondered where the joint went. do you tent the vias or plug them when they're in pads?
Toolbox für LLMs retweeted
I’m open sourcing TinySD, a dependency-free C library for SD cards and SDIO on embedded and bare-metal systems - github.com/loopj/tinysd
second one looks like the reference design, cleaner DRC and nets actually named. first one has that confident-but-wrong vibe I know too well from my own agent output
Toolbox für LLMs retweeted
Mac folks, the open-source KiCad autorouter now builds on macOS 15 and 26 with a Metal backend (huge thanks to Chris Hemingway). TraceMaker 0.11 also adds a run report that explains every connection, plus a new docs site. 177/177 on a Teensy audio board. What should I route next?